1. Field of the Invention
The present invention relates generally to split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications.
More particularly, the present invention relates to split gate field effect transistor (FET) devices with enhanced properties, as employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having formed therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device employed within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an inter-gate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce charge, reduce charge or sense charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within non-volatile semiconductor integrated circuit microelectronic fabrications split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to enhanced programming speed properties and enhanced erasing speed properties.
It is thus towards the goal of providing for use within semiconductor integrated circuit microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic memory fabrications, split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to enhanced programming speed properties and enhanced erasing speed properties, that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic fabrications, associated semiconductor integrated circuit microelectronic devices formed therein, methods for fabrication thereof and methods for operation thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
For example, Sung et al., in U.S. Pat. No. 6,005,809, discloses a method for programming within a semiconductor integrated circuit microelectronic fabrication a split gate field effect transistor (FET) device with enhanced programming speed properties and a method for erasing within the semiconductor integrated circuit microelectronic fabrication the split gate field effect transistor (FET) device with enhanced erasing speed properties, while simultaneously enhancing a cycling endurance property of the split gate field effect transistor (FET) device. To realize the enhanced programming speed properties, the programming method employs applying within the split gate field effect transistor (FET) device a simultaneous first positive voltage to a control gate electrode, a first moderately negative voltage to a semiconductor substrate and a first slightly positive voltage to a drain region in order to establish a constant programming current, and then applying a second positive voltage to a source region for programming purposes. Similarly, to realize the enhanced erasing speed, the erasing method employs applying within the split gate field effect transistor (FET) device a large positive voltage to the control gate electrode, the first moderately negative voltage to the semiconductor substrate and a second moderately negative voltage to the source region.
In addition, Chang, in U.S. Pat. No. 6,043,530, discloses an electrically erasable programmable read only memory (EEPROM) device that may be both programmed and read while employing low currents for both programming operations and erasing operations. The electrically erasable programmable read only memory (EEPROM) device is fabricated with a structure generally analogous with a stacked gate field effect transistor (FET) device, but with a control gate of width less than a floating gate width and centered within the floating gate width, and further wherein there is employed adjacent both the floating gate and the control gate, but spaced further from the control gate than the floating gate, a polysilicon sidewall spacer employed as an erasing gate electrode.
Finally, Houdt et al., in U.S. Pat. No. 6,058,043, discloses a non-volatile semiconductor integrated circuit microelectronic memory fabrication device, and a method for fabricating the non-volatile semiconductor integrated circuit microelectronic memory fabrication device, wherein the non-volatile semiconductor integrated circuit microelectronic memory fabrication device exhibits both enhanced programming properties and enhanced erasing properties while employing particularly low operating voltages and particularly low operating powers and while further avoiding stress induced leakage current (SILC) losses within the non-volatile semiconductor integrated circuit microelectronic memory fabrication device. To realize the foregoing objects, the non-volatile semiconductor integrated circuit microelectronic memory fabrication device is fabricated with a structure generally analogous with a split gate field effect transistor (FET) device structure, but wherein there is provided an additional programming gate electrode: (1) vertically spaced from and capacitively coupled to a floating gate electrode within the non-volatile semiconductor integrated circuit microelectronic memory fabrication device; and (2) laterally spaced from a control gate electrode within the non-volatile semiconductor integrated circuit microelectronic memory fabrication device.
Desirable within the art of non-volatile semiconductor integrated circuit microelectronic fabrication, and in particular within the art of non-volatile semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for forming split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to enhanced programming speed properties and enhanced erasing speed properties.
It is towards the foregoing objects that the present invention is directed.
A first object of the present invention is to provide for use within a semiconductor integrated circuit microelectronic fabrication a split gate field effect transistor (FET) device, and a method for fabricating the split gate field effect transistor (FET) device.
A second object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device in accord with the first object of the present invention, wherein the split gate field effect transistor (FET) device is fabricated with enhanced properties.
A third object of the present invention is to provide the split gate field effect transistor (FET) device and the method for fabricating the split gate field effect transistor (FET) device i n accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device. To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a doped polysilicon floating gate electrode, where the doped polysilicon floating gate electrode has a higher dopant concentration in a central annular portion of the doped polysilicon floating gate electrode than in a peripheral annular portion of the doped polysilicon floating gate electrode. There is then formed over the doped polysilicon floating gate electrode an inter-gate electrode dielectric layer. There is then formed over the inter-gate electrode dielectric layer and covering at least a portion of the doped polysilicon floating gate electrode a control gate electrode. Finally, there is also formed into the semiconductor substrate a pair of source/drain regions which define within the semiconductor substrate a floating gate electrode channel with respect to the doped polysilicon floating gate electrode and an adjoining control gate electrode channel with respect to the control gate electrode.
The method of the present invention contemplates a split gate field effect transistor (FET) device which may be fabricated employing the method of the present invention.
The present invention provides: (1) a method for fabricating within a semiconductor integrated circuit microelectronic fabrication, and in particular within a non-volatile semiconductor integrated circuit microelectronic memory fabrication, a split gate field effect transistor (FET) device; and (2) the split gate field effect transistor (FET) device fabricated employing the method, where the split gate field effect transistor (FET) device is fabricated with enhanced properties, such as but not limited to enhanced programming speed properties and enhanced erasing speed properties. The present invention realizes the foregoing objects by employing when fabricating a split gate field effect transistor (FET) device a doped polysilicon floating gate electrode, where the doped polysilicon floating gate electrode has a higher dopant concentration in a central annular portion of the doped polysilicon floating gate electrode than in a peripheral annular portion of the doped polysilicon floating gate electrode. By employing the higher dopant concentration in the central annular portion of the doped polysilicon floating gate electrode there may be realized within the split gate field effect transistor (FET) device enhanced coupling, in particular to a source/drain region formed within a semiconductor substrate beneath the doped polysilicon floating gate electrode, and thus enhanced programming speed properties within the split gate field effect transistor (FET) device. By employing the lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode, there is provided enhanced dimensional control when forming within the split gate field effect transistor (FET) device an inter-gate electrode dielectric layer while employing a thermal oxidation method which consumes part of the doped polysilicon floating gate electrode, and thus there is similarly also provided enhanced erasing speed properties within the split gate field effect transistor (FET) device.
The split gate field effect transistor (FET) device fabricated in accord with the present invention is readily commercially implemented. A split gate field effect transistor (FET) device fabricated in accord with the present invention employs methods and materials as are generally known in the art of emiconductor integrated circuit microelectronic fabrication, including but not limited to non-volatile semiconductor integrated circuit microelectronic memory fabrication, but employed within the context of a novel ordering and sequencing of process steps and materials fabrication to provide the split gate field effect transistor (FET) device in accord with the present invention. Since it is thus a novel ordering and sequencing of process steps and materials fabrication that provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.